DESIGN IP MERGE (SYSTEM CHIP INTEGRATION)
●Mere designs with different DBU
●Automatic design IP (cells) merge : name and priority based
Naming Option : prefix, postfix, rename only necessary, name mapping file and skip empty
●GUI based interactive IP merge
Switch cells from different designs
Log switch map and load switch map
●Layer Options
Visible layer only, top layer only and layer map
DESIGN CONSOLIDATION
●Consolidate identical via and standard cells, reduce GDSII/OASIS file size
●Hierarchy options
FAST BOOLEAN
●Support multiple boolean operation with single expression
((L13_P0 SIZING 0.1) AND (L16_P0 NOT L18_P0))OR (L13_P0 XOR L17_P0)
●Directly create shapes on original design